Coupling capacitance reduction

ABSTRACT

A method for reducing the coupling capacitance between adjacent electrically conductive interconnect lines of an integrated circuit. An electrically conductive layer is deposited and etched to produce electrically conductive interconnect lines having negatively sloped sidewalls. An insulating layer is deposited on the electrically conductive interconnect lines using a directional deposition to create a void between and directly adjacent electrically conductive interconnect lines. The void has a substantially lower dielectric constant than the material of the insulating layer, which reduces the coupling capacitance between adjacent electrically conductive interconnect lines.

FIELD

[0001] This invention relates generally to the field of integratedcircuit fabrication, and in particular the invention relates to reducingthe coupling capacitance between closely spaced electrically conductiveinterconnect lines, or in other words reducing the effective dielectricconstant of the material between closely spaced electrically conductiveinterconnect lines.

BACKGROUND

[0002] During fabrication of an integrated circuit, a variety of layersof electrically insulating materials and electrically conductingmaterials are typically deposited on a substrate. The layers arepatterned by selectively removing portions of the layers, to form thedesired electrical circuits. The need for faster and more complexintegrated circuits provides incentive to decrease the size of theintegrated circuits. As the size of the integrated circuit decreases,the size of the electrically conductive interconnects between thevarious components of the integrated circuit also tends to decrease. Forproper performance of the integrated circuit, it is desirable tomaintain high reliability and low electrical resistance while decreasingboth the size of the electrical interconnects and the spacing betweenadjacent electrical interconnects.

[0003] Highly conductive materials, such as metals, are often used forforming the electrically conductive interconnect lines of integratedcircuits. As the size of and spacing between the electrically conductiveinterconnect lines decreases, the capacitance between closely spacedinterconnects tends to increase, causing a generally commensurateincrease in cross talk and power dissipation between adjacentinterconnect lines. Cross talk is the signal interference betweenelectrically conductive interconnect lines, which tends to adverselyaffect signal integrity and signal strength. Power dissipation is thedynamic power drained by unwanted capacitance charging and dischargingin a circuit.

[0004] What is needed, therefore, is a method for reducing couplingcapacitance between adjacent electrically conductive interconnect linesin an integrated circuit.

SUMMARY

[0005] These and other needs are provided by a method for reducing thecoupling capacitance between electrically conductive interconnect linesof an integrated circuit. A conductive layer is deposited on asubstrate, and etched to define electrically conductive interconnectlines having negatively sloped sidewalls. The negatively slopingsidewalls of adjacent electrically conductive interconnect lines formundercut gaps in the conductive layer. An insulating layer is depositedon the etched conductive layer using a directional physical vapordeposition to cover the undercut gaps and form a void in each of theundercut gaps. The void is directly adjacent the negative slopingsidewalls of adjacent electrically conductive interconnect lines.

[0006] In another aspect the invention provides an integrated circuithaving closely spaced electrically conductive interconnect lines. A voidis formed between and directly adjacent undercut sidewalls of adjacentelectrically conductive interconnect lines. The void preferably has adielectric constant that is less than about two.

[0007] An advantage of the invention is that it provides an integratedcircuit having air gaps between electrically conductive interconnectlines so that more closely spaced interconnect lines can be provided ona substrate surface. Furthermore, the dielectric constant of the voidbetween adjacent interconnect lines tends to be substantially lower thanthose of the insulating materials that are typically used, such assilicon oxide. Because of the negatively sloping sidewalls of theadjacent interconnect lines, the void space in the gap is preferablyrelatively high, resulting in a relatively small effective dielectricconstant, which in turn results in a substantially lower effectivecapacitance between adjacent electrically conductive interconnect lines.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Further advantages of the invention are apparent by reference tothe detailed description when considered in conjunction with thefigures, which are not to scale so as to more clearly show the details,wherein like reference numbers indicate like elements throughout theseveral views, and wherein:

[0009]FIG. 1 is a cross sectional view of an electrically conductivelayer on a substrate,

[0010]FIG. 2 is a cross sectional view of the electrically conductivelayer on a substrate with a patterned layer of photoresist,

[0011]FIG. 3 is a cross sectional view of an etched electricallyconductive layer on a substrate,

[0012]FIG. 4 is a cross sectional view of negatively sloped sidewalls ofadjacent electrically conductive interconnect lines,

[0013]FIG. 5 is a cross sectional view of a layer sealing a void betweenadjacent electrically conductive interconnect lines, and

[0014]FIG. 4 is a cross sectional view of the planarized layer over thevoid.

DETAILED DESCRIPTION

[0015] Referring now to FIG. 1, a method is provided for reducing thecoupling capacitance between the closely spaced electrically conductiveinterconnect lines of an integrated circuit 10. The integrated circuit10 preferably includes one or more active or passive elements that areelectrically connected by electrically conductive interconnect lines Anelectrically conductive material such as gold, aluminum, copper, tin,tantalum, titanium, platinum, tungsten, molybdenum, polysilicon, or amixture or alloy of two or more of the foregoing is deposited on asubstrate 12 to provide an electrically conductive layer 14. Theelectrically conductive layer 14 is preferably substantially evenlydeposited over the whole surface of the substrate 12. The substrate 12may further comprise a plurality of various layers. Most preferably, thetopmost layer of the substrate 12 on which the electrically conductivelayer 14 is deposited is a non electrically conductive, or insulatinglayer.

[0016] Referring now to FIG. 2, a masking layer 16, such as photoresist,is deposited on the conductive layer 14. The masking layer 16 ispreferably patterned using conventional photolithography techniques toprovide an opening 18 in the masking layer 16, which opening 18corresponds to the spacing between adjacent interconnect lines that areto be formed in the conductive layer 14.

[0017] As illustrated in FIG. 3, gap 20 between adjacent electricallyconductive interconnect lines is formed in the conductive layer 14 by aprocess such as plasma etching the conductive layer 14 through theopening 18 in the masking layer 16. Etching of the conductive layer 14is preferably conducted in a manner whereby the sidewalls 22 of the gap20 have a negative slope, or in other words, where the sidewalls 22 ofthe gap 20 are closer together at the top of the gap 20 than they are atthe bottom of the gap 20.

[0018] Without being bound to a particular method of formation of thegap 20, or a particular theory of how the negative slope of thesidewalls 22 of the gap 20 are formed, the gap 20 may be plasma etchedin the absence of a magnetic field. During an initial etching period,polymer forming gases, such as halogenated methane and the like are usedto form polymeric substances on the sidewalls 22 of the conductive layer14 as they start to be formed, thereby passivating the upper portions ofthe sidewalls 22 so that boron halide species such as BCl₃anisotropically etch the conductive layer 14. However, unlikeconventional etching processes, after about ten to about fifteen secondsinto the etching process, the plasma chamber is purposefully depleted ofpolymer forming gases so that the lower portions of the sidewalls 22 ofthe conductive layer 14 are not passivated.

[0019] At this point in the etching process, the conductive layer 14 isetched isotropically, resulting in undercut regions and negativelysloping sidewalls 22 as illustrated in FIG. 3. The process produces agap 20 in the conductive layer 14, where the width 24 at the top of thegap 20 is substantially smaller than the width 26 at the bottom of thegap 20. The etching process thus produces ledges or overhangs 28 in theconductive layer 14 at the top of the gap 20, as depicted in FIG. 4.

[0020] Regardless of the exact process used to form the overhangs 28 inthe conductive layer 14, the overhangs 28 preferably enable theformation of a sealed void 34 in the conductive layer 14, as depicted inFIG. 5. A dielectric layer 30 is preferably deposited on top of theetched conductive layer 14 under conditions sufficient to form the void34 in the gap 20. The dielectric layer 30 is preferably a layer ofsubstantially non electrically conductive material such as, but notlimited to silicon nitride, silicon oxide such as silicon dioxide, boronnitride, and silicon carbide. A particularly preferred dielectric layer30 is a silicon oxide layer deposited with a modified silane physicalvapor deposition process.

[0021] The deposition reactor in which the dielectric layer 30 isdeposited is preferably detuned and highly directional to provide poorstep coverage of the dielectric layer 30 over the gap 20 in theconductive layer 14. Accordingly, a deposit 32 of the dielectricmaterial may be deposited in the gap 20. However, the portions of gap 20directly adjacent the sidewalls 22 of the conductive layer 14 are filledwith the void 34 created in the gap 20. In other words, the dielectricmaterial 32 formed at the bottom of the gap 20 preferably does notsubstantially contact the sidewalls 22 of the conductive layer 14.

[0022] Most of the void 34 is not filled with any solid material. Thevoid 34 preferably extends substantially completely across the gap 20between the negatively sloping sidewalls 22 of the gap 20, as depictedin FIG. 5. In other words, there is preferably substantially nodeposited material on the negatively sloped sidewalls 22, or on asubstantial portion of the substrate 12 at the bottom of the gap 20.Thus, according to the method of the present invention, it is preferredthat a minimal amount of material be deposited within the gap 20, andthat the void 34 comprise a relatively large portion of the gap 20.However, the deposited dielectric material 32 may contact the layer 30of dielectric material, as depicted in FIG. 6.

[0023] The void 34 may be filled with any one of a number of gases, suchas the precursor gases used during the deposition process whereby thedielectric layer 30 was formed. Most preferably the void 34 is filledwith air. By filling the gap 20 between the interconnect lines formed inthe conductive layer 14 with a gas that has a dielectric constant thatis preferably less than the dielectric constant of the insulatingmaterial used to form the dielectric layer 30, which for the materialsmost commonly used is no less than about two, the capacitive couplingbetween adjacent interconnect lines is preferably commensuratelyreduced. The effective dielectric constant of the void 34 is preferablybetween about one and about one and a half. The gas within the void 34may be at a pressure that is alternately greater than, less than, orsubstantially equal to atmospheric pressure.

[0024] After depositing the dielectric layer 30 on the etched conductivelayer 14, the dielectric layer 30 is preferably planarized, such as witha chemical mechanical polish, as depicted in FIG. 6. Additional layersmay be selectively deposited on the planarized dielectric layer 30 andthe process of etching the layers is repeated to create an integratedcircuit having relatively low coupling capacitance between adjacentinterconnect lines.

[0025] The foregoing description of preferred embodiments for thisinvention have been presented for purposes of illustration anddescription. They are not intended to be exhaustive or to limit theinvention to the precise form disclosed. Obvious modifications orvariations are possible in light of the above teachings. The embodimentsare chosen and described in an effort to provide the best illustrationsof the principles of the invention and its practical application, and tothereby enable one of ordinary skill in the art to utilize the inventionin various embodiments and with various modifications as is suited tothe particular use contemplated. All such modifications and variationsare within the scope of the invention as determined by the appendedclaims when interpreted in accordance with the breadth to which they arefairly, legally, and equitably entitled.

What is claimed is:
 1. A method for reducing the coupling capacitancebetween electrically conductive interconnect lines of an integratedcircuit, the method comprising the steps of: depositing a conductivelayer on a substrate, etching the conductive layer to define theelectrically conductive interconnect lines, where the electricallyconductive interconnect lines have sidewalls with negative slopes, thenegatively sloping sidewalls of adjacent electrically conductiveinterconnect lines forming undercut gaps in the conductive layer, anddepositing an insulating layer on the etched conductive layer using adirectional deposition to cover the undercut gaps and to form a void ineach of the undercut gaps, where the void is directly adjacent thenegative sloping sidewalls of adjacent electrically conductiveinterconnect lines.
 2. The method of claim 1 wherein the void is filledwith air.
 3. The method of claim 1 further comprising planarizing theinsulating layer with a chemical mechanical polishing process.
 4. Themethod of claim 1 wherein the insulating layer comprises silicon oxideformed in a silane process.
 5. The method of claim 1 wherein thedielectric constant of the void between adjacent electrically conductiveinterconnect lines is less than about two.
 6. The method of claim 1wherein the etching step comprises etching the conductive layer with aplasma containing a polymerizing gas for no more than about fifteenseconds and then substantially removing the polymerizing gas from theplasma while etching of the conductive layer is completed.
 7. Anintegrated circuit, the improvement comprising electrically conductiveinterconnect lines formed according to the method of claim
 1. 8. Anintegrated circuit having closely spaced electrically conductiveinterconnect lines, wherein the improvement comprises a void formedbetween and directly adjacent undercut sidewalls of adjacentelectrically conductive interconnect lines, the void having an effectivedielectric constant that is less than about two.
 9. The integratedcircuit of claim 8 wherein the void is bounded at a top of the void by adielectric layer that is planarized using a chemical mechanical polish.10. The integrated circuit of claim 9 wherein the dielectric layercomprises silicon oxide.
 11. The integrated circuit of claim 8 whereinthe electrically conductive layer is formed on an insulating layer. 12.The integrated circuit of claim 8 wherein the conductive layer is etchedwith a plasma containing a polymerizing gas for no more than aboutfifteen seconds and then the polymerizing gas is substantially removedfrom the plasma while etching of the conductive layer is completed. 13.The integrated circuit of claim 8 wherein a dielectric layer isdeposited on the etched conductive layer with a direction depositionthat substantially preserves the void between adjacent electricallyconductive interconnect lines.
 14. A method for reducing the capacitancebetween adjacent electrically conductive interconnect lines of anintegrated circuit, the method comprising the steps of: depositing asubstantially continuous conductive layer on a substrate, etching theconductive layer to define the electrically conductive interconnectlines, where the electrically conductive interconnect lines havesidewalls with negative slopes, the negatively sloping sidewalls ofadjacent electrically conductive interconnect lines forming undercutgaps in the conductive layer, depositing an insulating layer on theetched conductive layer using a directional physical vapor deposition tocover the undercut gaps and to form a void in each of the undercut gaps,where the void is directly adjacent the negative sloping sidewalls ofadjacent electrically conductive interconnect lines, and planarizing theinsulating layer with a chemical mechanical polishing process, where thevoid between adjacent electrically conductive interconnect lines has aneffective dielectric constant that is less than about two.
 15. Themethod of claim 14 wherein the void contains air.
 16. The method ofclaim 14 wherein the insulating layer comprises silicon oxide.
 17. Themethod of claim 14 wherein the etching step comprises etching theconductive layer with a plasma containing a polymerizing gas for no morethan about fifteen seconds and then substantially removing thepolymerizing gas from the plasma while etching of the conductive layeris completed.
 18. An integrated circuit, the improvement comprisingelectrically conductive interconnect lines formed according to themethod of claim 14.